Back in the 70s, the use of “high level languages” (algol, cobol, C) and compilers had become common practice for general computing. Back in those days, one also dreamed about a “silicon compiler” to “compile” a high level language to a hardware description. Since then, many methods and tools have been developed to aid in the design of digital hardware.
Today, hardware designs are typically coded in RTL languages like Verilog, SystemVerilog and VHDL. This is still quite different from the high level programming languages due to all the design detail that must be expressed in these RTL languages.
Only since a few years, High Level Synthesis enables the use of the more familiar high level languages for digital hardware design.
We have used the Catapult™ tool of Mentor Graphics (a Siemens company). With this tool, a C++ description can be compiled into digital hardware.
In the presentation, I will illustrate how to bridge the sequential nature of C++ and the inherent massively parallel nature of digital logic.
As we are all true Coders, I will use C++ code samples to illustrate how a certain style of C++ coding enables Catapult to generate hardware. The behavior of basic operations differs depending on regular software compilation or HLS compilation. Therefore, the same code can be viewed as “software” or as “hardware”. Again using code samples, we will see how to “view” the same code from a software perspective and from a hardware perspective.
Once we have built our basic signaling blocks and compositions, I will spend only a few minutes on the consequences for the entire project: unit test setup, digital simulations and hardware-in-the-loop testing. That is where the unified coding language really enables creativity and enables efficient design approaches.
So, today, the silicon compiler has become a reality.
Bram's slides are now available.
By: Bram Riemens